1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having a triple well (tub) structure.
2. Description of the Prior Art
When a dynamic random access memory (DRAM) is fabricated utilizing a p-type substrate by a conventional method, an n-channel MOS transistor for a memory cell section and an n-channel and p-channel MOS transistors for a peripheral circuit section are sometimes formed in different wells. Such a structure has various advantages in that: any noise caused in the peripheral circuit section does not affect the memory cell section; a substrate bias of the memory cell section can be controlled independently of the peripheral circuit section; a short-channel effect of the transistor for the peripheral circuit section can easily be controlled, and a substrate bias generating circuit can be made smaller.
However, in order to form an n-channel MOS transistor for a memory cell section and an n-channel and p-channel MOS transistors for a peripheral circuit section in different wells, a p-well of the memory cell section must be separated from the p-type silicon substrate. As a result, it is necessary to form an n-well which is larger in depth than the p-well so as to cover the p-well of the memory cell section, thereby forming a triple well structure.
Additionally, in a stacked DRAM, since a memory cell capacitor is formed over a switching transistor in each memory cell, the level of the memory cell section is higher than that of the surrounding area (the peripheral circuit section). Because of this change in level, it is sometimes difficult to interconnect the memory cell section and the peripheral circuit section through conductive lines (wirings). As a countermeasure to such a disadvantage, the level of the memory cell section only is made lower, so that the change in level made by the memory cell section and the peripheral circuit section is reduced.
In the above-mentioned conventional method of fabricating a semiconductor device, it is possible to reduce the change in level made by the memory cell section and the peripheral circuit section in order to prevent a disconnection (opening) and short on the conductive lines from occurring. However, this necessitates additional process steps of initially making the level of the semiconductor substrate lower and of forming a plurality of wells, so that there arises another problem in that the fabrication process becomes complicated.